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PE64905
Product Specification
Equivalent Circuit Model Description
Figure 18. Equivalent Circuit Model Schematic
The DTC Equivalent Circuit Model includes all
parasitic elements and is accurate in both Series
and Shunt configurations, reflecting physical circuit
behavior accurately and providing very close
correlation to measured data. It can easily be used
in circuit simulation programs. Most parameters are
state independent, and simple equations are
RF+
L S
C P
R P1
V P
R S
R P2
C S
C P
R P1
V M
L S
R P2
RF-
provided for the state dependent parameters.
The Tuning Core capacitance C S represents
capacitance between RF+ and RF- ports. It is
linearly proportional to state (0 to 31 in decimal) in
a discrete fashion. The Series Tuning Ratio is
defined as C Smax /C Smin .
RFGND
Table 8. Equivalent Circuit Model Parameters
Variable Equation (state = 0, 1, 2…31) Units
C S 0.129*state + 0.600 pF
R S
20/(state+20/(state+0.7)) + 0.7
?
C P represents the circuit and package parasitics
from RF ports to GND. In Shunt configuration the
total capacitance of the DTC is higher due to
parallel combination of C P and C S . In Series
configuration, C S and C P do not add in parallel and
the DTC appears as an impedance transformation
network.
R P1 7
R P2 10
C P 0.5
L S 0.27
Table 9. Equivalent Circuit Data
State
DTC Core
?
k ?
pF
nH
Parasitic inductance due to circuit and package is
modeled as L S and causes the apparent
capacitance of the DTC to increase with frequency
until it reaches Self Resonant Frequency (SRF).
The value of SRF depends on state and is
approximately inversely proportional to the square
root of capacitance.
The overall dissipative losses of the DTC are
modeled by R S , R P1 and R P2 resistors. The
parameter R S represents the Equivalent Series
Resistance (ESR) of the tuning core and is
dependent on state. R P1 and R P2 represent losses
due to the parasitic and biasing networks, and are
state-independent.
Table 7. Maximum Operating RF Voltage
Binary
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
Decimal
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
C s [pF]
0.60
0.73
0.86
0.99
1.12
1.25
1.37
1.50
1.63
1.76
1.89
2.02
2.15
2.28
2.41
2.54
2.66
2.79
2.92
3.05
3.18
R s [ ? ]
1.40
2.27
2.83
3.08
3.12
3.05
2.93
2.78
2.64
2.51
2.39
2.27
2.17
2.08
2.00
1.93
1.86
1.80
1.75
1.70
1.65
Condition
V P to V M
V P to RFGND
V M to RFGND
Limit
30 Vpk
30 Vpk
30 Vpk
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
21
22
23
24
25
26
27
28
29
30
31
3.31
3.44
3.57
3.70
3.83
3.95
4.08
4.21
4.34
4.47
4.60
1.61
1.57
1.54
1.51
1.48
1.45
1.42
1.40
1.37
1.35
1.33
?2011-2012 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0335-06
│ UltraCMOS ? RFIC Solutions
Page 8 of 11
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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